#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_CHIP_ESP32S3

comment "ESP32-S3 Configuration Options"

choice
	prompt "ESP32-S3 Chip Selection"
	default ARCH_CHIP_ESP32S3WROOM1

config ARCH_CHIP_ESP32S3WROOM1
	bool "ESP32-S3-WROOM-1"
	select ESP32S3_FLASH_4M
	select ARCH_HAVE_I2CRESET
	---help---
		Generic module with an embedded ESP32-S3.

config ARCH_CHIP_ESP32S3WROOM2
	bool "ESP32-S3-WROOM-2"
	select ESP32S3_FLASH_16M
	select ESP32S3_PSRAM_8M
	select ARCH_HAVE_I2CRESET
	---help---
		Generic module with an embedded ESP32-S3.

config ARCH_CHIP_ESP32S3MINI1
	bool "ESP32-S3-MINI-1"
	select ESP32S3_FLASH_8M
	select ARCH_HAVE_I2CRESET
	---help---
		Generic module with an embedded ESP32-S3.

endchoice # ESP32-S3 Chip Selection

config ESPRESSIF_CHIP_SERIES
	string
	default "esp32s3"

choice ESP32S3_DEFAULT_CPU_FREQ
	prompt "CPU frequency"
	default ESP32S3_DEFAULT_CPU_FREQ_240
	---help---
		CPU frequency to be set on application startup.

config ESP32S3_DEFAULT_CPU_FREQ_80
	bool "80 MHz"

config ESP32S3_DEFAULT_CPU_FREQ_160
	bool "160 MHz"

config ESP32S3_DEFAULT_CPU_FREQ_240
	bool "240 MHz"

endchoice # CPU frequency

config ESP32S3_DEFAULT_CPU_FREQ_MHZ
	int
	default 80 if ESP32S3_DEFAULT_CPU_FREQ_80
	default 160 if ESP32S3_DEFAULT_CPU_FREQ_160
	default 240 if ESP32S3_DEFAULT_CPU_FREQ_240

menu "Cache configuration"

choice
	prompt "Instruction cache size"
	default ESP32S3_INSTRUCTION_CACHE_16KB
	---help---
		Instruction cache size to be set on application startup.
		If you use 16KB instruction cache rather than 32KB instruction cache,
		then the other 16KB will be managed by heap allocator.

config ESP32S3_INSTRUCTION_CACHE_16KB
	bool "16KB"
	---help---
		Use 16KB of SRAM as Instruction Cache

config ESP32S3_INSTRUCTION_CACHE_32KB
	bool "32KB"
	---help---
		Use 32KB of SRAM as Instruction Cache

endchoice # Instruction cache size

config ESP32S3_INSTRUCTION_CACHE_SIZE
	hex
	default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
	default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB

choice ESP32S3_ICACHE_ASSOCIATED_WAYS
	prompt "Instruction cache associated ways"
	default ESP32S3_INSTRUCTION_CACHE_8WAYS
	---help---
		Instruction cache associated ways to be set on application startup.

config ESP32S3_INSTRUCTION_CACHE_4WAYS
	bool "4 ways"

config ESP32S3_INSTRUCTION_CACHE_8WAYS
	bool "8 ways"

endchoice # Instruction cache associated ways

config ESP32S3_ICACHE_ASSOCIATED_WAYS
	int
	default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
	default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS

choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
	prompt "Instruction cache line size"
	default ESP32S3_INSTRUCTION_CACHE_LINE_32B
	---help---
		Instruction cache line size to be set on application startup.

config ESP32S3_INSTRUCTION_CACHE_LINE_16B
	bool "16 Bytes"
	depends on ESP32S3_INSTRUCTION_CACHE_16KB

config ESP32S3_INSTRUCTION_CACHE_LINE_32B
	bool "32 Bytes"

endchoice # ESP32S3_INSTRUCTION_CACHE_LINE_SIZE

config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
	int
	default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
	default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B

choice
	prompt "Data cache size"
	default ESP32S3_DATA_CACHE_32KB
	---help---
		Data cache size to be set on application startup.
		If you use 32KB data cache rather than 64KB data cache,
		the other 32KB will be added to the heap.

config ESP32S3_DATA_CACHE_16KB
	bool "16KB"
	---help---
		Use 16KB of SRAM as Data Cache

config ESP32S3_DATA_CACHE_32KB
	bool "32KB"
	---help---
		Use 32KB of SRAM as Data Cache

config ESP32S3_DATA_CACHE_64KB
	bool "64KB"
	---help---
		Use 64KB of SRAM as Data Cache

endchoice # Data cache size

config ESP32S3_DATA_CACHE_SIZE
	hex
	# For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
	default 0x8000 if ESP32S3_DATA_CACHE_16KB
	default 0x8000 if ESP32S3_DATA_CACHE_32KB
	default 0x10000 if ESP32S3_DATA_CACHE_64KB

choice ESP32S3_DCACHE_ASSOCIATED_WAYS
	prompt "Data cache associated ways"
	default ESP32S3_DATA_CACHE_8WAYS
	---help---
		Data cache associated ways to be set on application startup.

config ESP32S3_DATA_CACHE_4WAYS
	bool "4 ways"

config ESP32S3_DATA_CACHE_8WAYS
	bool "8 ways"

endchoice # ESP32S3_DCACHE_ASSOCIATED_WAYS

config ESP32S3_DCACHE_ASSOCIATED_WAYS
	int
	default 4 if ESP32S3_DATA_CACHE_4WAYS
	default 8 if ESP32S3_DATA_CACHE_8WAYS

choice ESP32S3_DATA_CACHE_LINE_SIZE
	prompt "Data cache line size"
	default ESP32S3_DATA_CACHE_LINE_32B
	---help---
		Data cache line size to be set on application startup.

config ESP32S3_DATA_CACHE_LINE_16B
	bool "16 Bytes"
	depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB

config ESP32S3_DATA_CACHE_LINE_32B
	bool "32 Bytes"

config ESP32S3_DATA_CACHE_LINE_64B
	bool "64 Bytes"

endchoice # ESP32S3_DATA_CACHE_LINE_SIZE

config ESP32S3_DATA_CACHE_LINE_SIZE
	int
	default 16 if ESP32S3_DATA_CACHE_LINE_16B
	default 32 if ESP32S3_DATA_CACHE_LINE_32B
	default 64 if ESP32S3_DATA_CACHE_LINE_64B

endmenu # Cache config

config ESP32S3_ULP_COPROC_ENABLED
	bool "Enable Ultra Low Power (ULP) Coprocessor"
	default n
	---help---
		Set to 'y' if you plan to load a firmware for the coprocessor.

config ESP32S3_ULP_COPROC_RESERVE_MEM
	int
	prompt "RTC slow memory reserved for coprocessor" if ESP32S3_ULP_COPROC_ENABLED
	default 512 if ESP32S3_ULP_COPROC_ENABLED
	range 32 8176 if ESP32S3_ULP_COPROC_ENABLED
	default 0 if !ESP32S3_ULP_COPROC_ENABLED
	range 0 0 if !ESP32S3_ULP_COPROC_ENABLED
	---help---
		Bytes of memory to reserve for ULP coprocessor firmware & data.
		Data is reserved at the beginning of RTC slow memory.

config ESP32S3_FLASH_4M
	bool
	default n

config ESP32S3_FLASH_8M
	bool
	default n

config ESP32S3_FLASH_16M
	bool
	default n

config ESP32S3_FLASH_32M
	bool
	default n
	select ESP32S3_SPI_FLASH_USE_32BIT_ADDRESS

config ESP32S3_ESPTOOLPY_NO_STUB
	bool "Disable download stub"
	default n
	---help---
		The flasher tool sends a precompiled download stub first by default.
		That stub allows things like compressed downloads and more.
		Usually you should not need to disable that feature.
		It is only required to be disabled in certain scenarios when either
		Secure Boot V2 or Flash Encryption is enabled.

config ESP32S3_FLASH_DETECT
	bool "Auto-detect FLASH size"
	default y
	---help---
		Auto detect flash size when flashing.

config ESP32S3_PSRAM_8M
	bool
	default n

config ESP32S3_RUN_IRAM
	bool "Run from IRAM"
	default n
	---help---
		This loads all of NuttX inside IRAM. Used to test somewhat small
		images that can fit entirely in IRAM.

menu "ESP32-S3 Peripheral Selection"

source "arch/xtensa/src/common/espressif/Kconfig"

config ESP32S3_UART
	bool
	default n

config ESP32S3_TIMER
	bool
	default n

config ESP32S3_I2C
	bool
	default n

config ESP32S3_I2S
	bool "I2S"
	select I2S
	---help---
		See the Board Selection menu to configure the pins used by I2S.

if ESP32S3_I2S

config ESP32S3_I2S0
	bool "I2S 0"
	default n
	select ESP32S3_DMA
	select ESP32S3_GPIO_IRQ
	select SCHED_HPWORK

if ESP32S3_I2S0

config ESP32S3_I2S0_RX
	bool "Enable I2S receiver"
	default y
	---help---
		Enable I2S receiver (port 0)

config ESP32S3_I2S0_TX
	bool "Enable I2S transmitter"
	default y
	---help---
		Enable I2S transmitter (port 0)

choice
	prompt "I2S0 role"
	default ESP32S3_I2S0_ROLE_MASTER
	---help---
		Selects the operation role of the I2S0.

config ESP32S3_I2S0_ROLE_MASTER
	bool "Master"

config ESP32S3_I2S0_ROLE_SLAVE
	bool "Slave"

endchoice # I2S0 role

choice
	prompt "Bit width"
	default ESP32S3_I2S0_DATA_BIT_WIDTH_16BIT
	---help---
		Selects the valid data bits per sample.
		Note that this option may be overwritten by the audio
		according to the bit width of the file being played

config ESP32S3_I2S0_DATA_BIT_WIDTH_8BIT
	bool "8 bits"

config ESP32S3_I2S0_DATA_BIT_WIDTH_16BIT
	bool "16 bits"

config ESP32S3_I2S0_DATA_BIT_WIDTH_24BIT
	bool "24 bits"

config ESP32S3_I2S0_DATA_BIT_WIDTH_32BIT
	bool "32 bits"

endchoice # Bit width

config ESP32S3_I2S0_DATA_BIT_WIDTH
	int
	default 8 if ESP32S3_I2S0_DATA_BIT_WIDTH_8BIT
	default 16 if ESP32S3_I2S0_DATA_BIT_WIDTH_16BIT
	default 24 if ESP32S3_I2S0_DATA_BIT_WIDTH_24BIT
	default 32 if ESP32S3_I2S0_DATA_BIT_WIDTH_32BIT

config ESP32S3_I2S0_SAMPLE_RATE
	int "I2S0 sample rate"
	default 44100
	range 8000 48000
	---help---
		Selects the sample rate.
		Note that this option may be overwritten by the audio
		according to the bit width of the file being played

config ESP32S3_I2S0_BCLKPIN
	int "I2S0 BCLK pin"
	default 4
	range 0 33 if ESP32S3_I2S0_ROLE_MASTER
	range 0 39 if ESP32S3_I2S0_ROLE_SLAVE

config ESP32S3_I2S0_WSPIN
	int "I2S0 WS pin"
	default 5
	range 0 33 if ESP32S3_I2S0_ROLE_MASTER
	range 0 39 if ESP32S3_I2S0_ROLE_SLAVE

config ESP32S3_I2S0_DINPIN
	int "I2S0 DIN pin"
	depends on ESP32S3_I2S0_RX
	default 19
	range 0 39

config ESP32S3_I2S0_DOUTPIN
	int "I2S0 DOUT pin"
	depends on ESP32S3_I2S0_TX
	default 18
	range 0 33

config ESP32S3_I2S0_MCLK
	bool "Enable I2S Master Clock"
	depends on ESP32S3_I2S0_ROLE_MASTER
	default n
	---help---
		Enable I2S master clock

config ESP32S3_I2S0_MCLKPIN
	int "I2S MCLK pin"
	depends on ESP32S3_I2S0_MCLK
	default 0
	range 0 39

endif #ESP32S3_I2S0

config ESP32S3_I2S1
	bool "I2S 1"
	default n
	select ESP32S3_DMA
	select ESP32S3_GPIO_IRQ
	select SCHED_HPWORK

if ESP32S3_I2S1

config ESP32S3_I2S1_RX
	bool "Enable I2S receiver"
	default y
	---help---
		Enable I2S receiver (port 1)

config ESP32S3_I2S1_TX
	bool "Enable I2S transmitter"
	default y
	---help---
		Enable I2S transmitter (port 1)

choice
	prompt "I2S1 role"
	default ESP32S3_I2S1_ROLE_MASTER
	---help---
		Selects the operation role of the I2S1.

config ESP32S3_I2S1_ROLE_MASTER
	bool "Master"

config ESP32S3_I2S1_ROLE_SLAVE
	bool "Slave"

endchoice # I2S1 role

choice
	prompt "Bit width"
	default ESP32S3_I2S1_DATA_BIT_WIDTH_16BIT
	---help---
		Selects the valid data bits per sample.
		Note that this option may be overwritten by the audio
		according to the bit width of the file being played

config ESP32S3_I2S1_DATA_BIT_WIDTH_8BIT
	bool "8 bits"

config ESP32S3_I2S1_DATA_BIT_WIDTH_16BIT
	bool "16 bits"

config ESP32S3_I2S1_DATA_BIT_WIDTH_24BIT
	bool "24 bits"

config ESP32S3_I2S1_DATA_BIT_WIDTH_32BIT
	bool "32 bits"

endchoice

config ESP32S3_I2S1_DATA_BIT_WIDTH
	int
	default 8 if ESP32S3_I2S1_DATA_BIT_WIDTH_8BIT
	default 16 if ESP32S3_I2S1_DATA_BIT_WIDTH_16BIT
	default 24 if ESP32S3_I2S1_DATA_BIT_WIDTH_24BIT
	default 32 if ESP32S3_I2S1_DATA_BIT_WIDTH_32BIT

config ESP32S3_I2S1_SAMPLE_RATE
	int "I2S1 sample rate"
	default 44100
	range 8000 48000
	---help---
		Selects the sample rate.
		Note that this option may be overwritten by the audio
		according to the bit width of the file being played

config ESP32S3_I2S1_BCLKPIN
	int "I2S1 BCLK pin"
	default 22
	range 0 33 if ESP32S3_I2S1_ROLE_MASTER
	range 0 39 if ESP32S3_I2S1_ROLE_SLAVE

config ESP32S3_I2S1_WSPIN
	int "I2S1 WS pin"
	default 23
	range 0 33 if ESP32S3_I2S1_ROLE_MASTER
	range 0 39 if ESP32S3_I2S1_ROLE_SLAVE

config ESP32S3_I2S1_DINPIN
	int "I2S1 DIN pin"
	depends on ESP32S3_I2S1_RX
	default 26
	range 0 39

config ESP32S3_I2S1_DOUTPIN
	int "I2S1 DOUT pin"
	depends on ESP32S3_I2S1_TX
	default 25
	range 0 33

config ESP32S3_I2S1_MCLK
	bool "Enable I2S Master Clock"
	depends on ESP32S3_I2S1_ROLE_MASTER
	default n
	---help---
		Enable I2S master clock

config ESP32S3_I2S1_MCLKPIN
	int "I2S MCLK pin"
	depends on ESP32S3_I2S1_MCLK
	default 1
	range 0 39

endif #ESP32S3_I2S1

config I2S_DMADESC_NUM
	int "I2S DMA maximum number of descriptors"
	default 2
	---help---
		Configure the maximum number of out-link/in-link descriptors to
		be chained for a I2S DMA transfer.

endif #ESP32S3_I2S


config ESP32S3_SPI
	bool
	default n

config ESP32S3_WDT
	bool
	default n

config ESP32S3_EFUSE
	bool "EFUSE support"
	default n
	---help---
		Enable ESP32-S3 efuse support.

config ESP32S3_RNG
	bool "Random Number Generator (RNG)"
	default n
	select ARCH_HAVE_RNG
	---help---
		ESP32-S3 supports a RNG that passed on Dieharder test suite.

config ESP32S3_SPIRAM
	bool "SPI RAM Support"
	default n

config ESP32S3_SPI2
	bool "SPI 2"
	default n
	select ESP32S3_SPI
	select SPI
	select ESP32S3_GPIO_IRQ if SPI_SLAVE

config ESP32S3_SPI3
	bool "SPI 3"
	default n
	select ESP32S3_SPI
	select SPI
	select ESP32S3_GPIO_IRQ if SPI_SLAVE

config ESP32S3_DMA
	bool "General DMA (GDMA)"
	default n
	select ARCH_DMA

config ESP32S3_RTC
	bool "Real Time Clock (RTC)"
	default y

config ESP32S3_UART0
	bool "UART 0"
	default n
	select ESP32S3_UART
	select UART0_SERIALDRIVER
	select ARCH_HAVE_SERIAL_TERMIOS

config ESP32S3_UART1
	bool "UART 1"
	default n
	select ESP32S3_UART
	select UART1_SERIALDRIVER
	select ARCH_HAVE_SERIAL_TERMIOS

config ESP32S3_UART2
	bool "UART 2"
	default n
	select ESP32S3_UART
	select UART2_SERIALDRIVER
	select ARCH_HAVE_SERIAL_TERMIOS

config ESP32S3_WIRELESS
	bool
	default n
	select NET
	select ARCH_PHY_INTERRUPT
	select ESP32S3_RNG
	select ESP32S3_RT_TIMER
	select ESP32S3_TIMER0
	---help---
		Enable Wireless support

config ESP32S3_WIFI
	bool "Wi-Fi"
	default n
	select ESP32S3_WIRELESS
	---help---
		Enable Wi-Fi support

config ESP32S3_BLE
	bool "BLE"
	default n
	select ESP32S3_WIRELESS
	---help---
		Enable BLE support

config ESP32S3_I2C0
	bool "I2C 0"
	default n
	select ESP32S3_I2C
	select I2C

config ESP32S3_I2C1
	bool "I2C 1"
	default n
	select ESP32S3_I2C
	select I2C

config ESP32S3_TWAI
	bool "TWAI (CAN)"
	default n
	select CAN

config ESP32S3_LEDC
	bool "LEDC (PWM)"
	default n
	select PWM
	select ARCH_HAVE_PWM_MULTICHAN
	---help---
		Enable support to PWM on ESP32S3 using LEDC peripheral.

config ESP32S3_USBSERIAL
	bool "USB-Serial Driver"
	default n
	select OTHER_UART_SERIALDRIVER
	select ARCH_HAVE_SERIAL_TERMIOS

config ESP32S3_OTG
	bool "USB OTG"
	default n

config ESP32S3_TIMER0
	bool "54-bit Timer 0 (Group 0 Timer 0)"
	default n
	select ESP32S3_TIMER
	---help---
		Enables Timer 0

config ESP32S3_TIMER1
	bool "54-bit Timer 1 (Group 0 Timer 1)"
	default n
	select ESP32S3_TIMER
	---help---
		Enables Timer 1

config ESP32S3_TIMER2
	bool "54-bit Timer 2 (Group 1 Timer 0)"
	default n
	select ESP32S3_TIMER
	---help---
		Enables Timer 2

config ESP32S3_TIMER3
	bool "54-bit Timer 3 (Group 1 Timer 1)"
	default n
	select ESP32S3_TIMER
	---help---
		Enables Timer 3

config ESP32S3_MWDT0
	bool "Main System Watchdog Timer (Group 0)"
	default n
	select ESP32S3_WDT
	---help---
		Includes MWDT0. This watchdog timer is part of the Group 0
		timer submodule.

config ESP32S3_MWDT1
	bool "Main System Watchdog Timer (Group 1)"
	default n
	select ESP32S3_WDT
	---help---
		Includes MWDT1. This watchdog timer is part of the Group 0
		timer submodule.

config ESP32S3_RWDT
	bool "RTC Watchdog Timer"
	default n
	select ESP32S3_WDT
	select ESP32S3_RTCIO_IRQ
	---help---
		Includes RWDT. This watchdog timer is from the RTC module.
		When it is selected, if the developer sets it to reset on expiration
		it will reset Main System and the RTC module. If you don't want
		to have the RTC module reset, please, use the Timers' Module WDTs.
		They will only reset Main System.

config ESP32S3_XTWDT
	bool "XTAL32K Watchdog Timer"
	depends on ESP32S3_RTC_CLK_EXT_OSC || ESP32S3_RTC_CLK_EXT_XTAL
	default n
	select ESP32S3_WDT
	select ESP32S3_RTCIO_IRQ
	---help---
		Includes XTWDT. This watchdog timer monitors the status of the
		external 32 kHz crystal oscillator (XTAL32K). When XTAL32K_CLK works
		as the clock source of RTC_SLOW_CLK and it stops oscillating, the
		XTAL32K watchdog timer first switches to BACKUP32K_CLK derived from
		RC_SLOW_CLK (if ESP32S3_XTWDT_BACKUP_CLK_ENABLE) and, then, generates
		an interrupt that could be captured by WDIOC_CAPTURE.

config ESP32S3_XTWDT_BACKUP_CLK_ENABLE
	bool "Automatically switch to BACKUP32K_CLK when timer expires"
	depends on ESP32S3_XTWDT
	default y
	help
		Enable this to automatically switch to BACKUP32K_CLK as the source of
		RTC_SLOW_CLK when the watchdog timer expires.

config ESP32S3_RT_TIMER
	bool "Real-Time Timer"
	default n
	---help---
		Real-Time Timer is relying upon the Systimer 1.

config ESP32S3_WCL
	bool "World Controller"
	default n
	select ARCH_USE_MPU
	select XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS if BUILD_PROTECTED

config ESP32S3_LCD
	bool "LCD"
	default n
	select DRIVERS_VIDEO
	select VIDEO_FB
	select FB_UPDATE
	help
	---help---
		LCD controller that outputs parallel data and supports RGB interface.

endmenu # ESP32-S3 Peripheral Selection

menuconfig ESP32S3_WIFI_BT_COEXIST
	bool "Wi-Fi and BT coexist"
	default y if ESP32S3_WIFI && ESP32S3_BLE
	default n
	depends on ESP32S3_WIFI && ESP32S3_BLE
	select ESP32S3_WIFI_STA_DISCONNECT_PM

menu "Interrupt Configuration"

config ESP32S3_IRAM_ISR_DEBUG
	bool "Enable debugging of the IRAM-enabled interrupts"
	default n
	---help---
		This option enables keeping track of the IRAM-enabled interrupts by
		registering its execution when non-IRAM interrupts are disabled. It
		keeps track of the IRQ executed and register how many times since
		boot it was executed.

endmenu # Interrupt Configuration

menu "SPI RAM Configuration"
	depends on ESP32S3_SPIRAM

choice ESP32S3_SPIRAM_MODE
	prompt "Mode (QUAD/OCT) of SPI RAM chip"
	default ESP32S3_SPIRAM_MODE_QUAD

config ESP32S3_SPIRAM_MODE_QUAD
	bool "Quad Mode PSRAM"

config ESP32S3_SPIRAM_MODE_OCT
	bool "Octal Mode PSRAM"

endchoice # ESP32S3_SPIRAM_MODE

config ESP32S3_DEFAULT_PSRAM_CLK_IO
	int "PSRAM CLK pin"
	default 30

config ESP32S3_DEFAULT_PSRAM_CS_IO
	int "PSRAM CS pin"
	default 26

choice ESP32S3_SPIRAM_TYPE
	prompt "Type of SPI RAM chip in use"
	default ESP32S3_SPIRAM_TYPE_AUTO

config ESP32S3_SPIRAM_TYPE_AUTO
	bool "Auto-detect"

config ESP32S3_SPIRAM_TYPE_ESPPSRAM16
	bool "ESP-PSRAM16 or APS1604"

config ESP32S3_SPIRAM_TYPE_ESPPSRAM32
	bool "ESP-PSRAM32 or IS25WP032"

config ESP32S3_SPIRAM_TYPE_ESPPSRAM64
	bool "ESP-PSRAM64, LY68L6400 or APS6408"

endchoice # ESP32S3_SPIRAM_TYPE

config ESP32S3_SPIRAM_SIZE
	int
	default -1 if ESP32S3_SPIRAM_TYPE_AUTO
	default 2097152 if ESP32S3_SPIRAM_TYPE_ESPPSRAM16
	default 4194304 if ESP32S3_SPIRAM_TYPE_ESPPSRAM32
	default 8388608 if ESP32S3_SPIRAM_TYPE_ESPPSRAM64
	default 16777216 if ESP32S3_SPIRAM_TYPE_ESPPSRAM128
	default 33554432 if ESP32S3_SPIRAM_TYPE_ESPPSRAM256
	default 0

config ESP32S3_SPIRAM_FETCH_INSTRUCTIONS
	bool "Cache fetch instructions from SPI RAM"
	default n
	---help---
		If enabled, instruction in flash will be copied into SPIRAM.
		If ESP32S3_SPIRAM_RODATA is also enabled, you can run the instruction
		when erasing or programming the flash.

config ESP32S3_SPIRAM_RODATA
	bool "Cache load read only data from SPI RAM"
	default n
	---help---
		If enabled, rodata in flash will be copied into SPIRAM.
		If ESP32S3_SPIRAM_FETCH_INSTRUCTIONS is also enabled,
		you can run the instruction when erasing or programming the
		flash.

choice ESP32S3_SPIRAM_SPEED
	prompt "Set RAM clock speed"
	default ESP32S3_SPIRAM_SPEED_40M
	---help---
		Select the speed for the SPI RAM chip.

config ESP32S3_SPIRAM_SPEED_40M
	bool "40MHz clock speed"

config ESP32S3_SPIRAM_SPEED_80M
	bool "80MHz clock speed"

config ESP32S3_SPIRAM_SPEED_120M
	bool "120MHz clock speed"
	depends on ESP32S3_SPIRAM_MODE_QUAD

endchoice # ESP32S3_SPIRAM_SPEED

config ESP32S3_SPIRAM_SPEED
	int
	default 120 if ESP32S3_SPIRAM_SPEED_120M
	default 80 if ESP32S3_SPIRAM_SPEED_80M
	default 40 if ESP32S3_SPIRAM_SPEED_40M

config ESP32S3_SPIRAM_ECC_ENABLE
	bool "Enable SPI RAM ECC"
	default n
	depends on ESP32S3_SPIRAM_MODE_OCT
	---help---
		Enable MSPI Error-Correcting Code function when accessing SPIRAM.
		If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.

config ESP32S3_SPIRAM_BOOT_INIT
	bool "Initialize SPI RAM during startup"
	depends on ESP32S3_SPIRAM
	default y
	---help---
		If this is enabled, the SPI RAM will be enabled during initial
		boot. Unless you have specific requirements, you'll want to leave
		this enabled so memory allocated during boot-up can also be
		placed in SPI RAM.

config ESP32S3_SPIRAM_IGNORE_NOTFOUND
	bool "Ignore PSRAM when not found"
	default n
	depends on ESP32S3_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA
	---help---
		Normally, if psram initialization is enabled during compile time
		but not found at runtime, it is seen as an error making the CPU
		panic. If this is enabled, booting will complete but no PSRAM
		will be available.

endmenu # SPI RAM Configuration

menu "Memory Configuration"

comment "Additional Heaps"

choice ESP32S3_SPIRAM_HEAP
	prompt "SPI RAM heap function"
	default ESP32S3_SPIRAM_COMMON_HEAP if BUILD_FLAT
	default ESP32S3_SPIRAM_USER_HEAP if BUILD_PROTECTED
	depends on ESP32S3_SPIRAM
	---help---
		Select how the SPI RAM will be used as heap.

config ESP32S3_SPIRAM_COMMON_HEAP
	bool "Additional region to kernel heap"

config ESP32S3_SPIRAM_USER_HEAP
	bool "Separated userspace heap"
	select MM_KERNEL_HEAP

endchoice # ESP32S3_SPIRAM_HEAP

config ESP32S3_RTC_HEAP
	bool "Use the RTC memory as a separate heap"
	select ARCH_HAVE_EXTRA_HEAPS
	default n

config ESP32S3_SPIRAM_MAP
	bool "Remap the size and offset of SPIRAM virtual address"
	depends on ESP32S3_SPIRAM
	default n

config ESP32S3_SPIRAM_VADDR_OFFSET
	hex "Map virtual address offset"
	default 0x30000
	depends on ESP32S3_SPIRAM_MAP
	range 0 0x1FF0000

config ESP32S3_SPIRAM_VADDR_MAP_SIZE
	hex "Map virtual address size"
	default 0x400000
	depends on ESP32S3_SPIRAM_MAP
	range 0x10000 0x2000000

config ESP32S3_SPIRAM_BANKSWITCH_ENABLE
	bool "Enable bank switching for external RAM"
	default n
	depends on ESP32S3_SPIRAM_MAP
	---help---
		The MMU table of ESP32-S3 is up to 512, and the page size of each MMU
		is 64KB. The MMU table can be used for mapping instructions and data.
		External RAM mapped into data space in 64 KB blocks no larger than 32MB.
		The hardware does support larger memories, but these have to be
		bank-switched in and out of this address space. Enabling this allows
		you to reserve some MMU pages for this, which allows the use of the
		esp32s3_himem api to manage these
		banks.

config SPIRAM_BANKSWITCH_RESERVE
	int "Amount of 64K pages to reserve for bank switching"
	depends on ESP32S3_SPIRAM_BANKSWITCH_ENABLE
	default 4
	range 1 256
	---help---
		Select the amount of banks reserved for bank switching. Note
		that the amount of RAM allocatable with malloc will decrease
		by 64KB for each page reserved here.
		Note that the amount of banks reserved is smaller than the number
		of 64KB blocks of configured external RAM mapped to the data space.
		Note that this reservation is only actually done if your
		program actually uses the himem API. Without any himem
		calls, the reservation is not done and the original amount
		of memory will be available.

endmenu # Memory Configuration

config ESP32S3_GPIO_IRQ
	bool "GPIO pin interrupts"
	default n
	---help---
		Enable support for interrupting GPIO pins.

config ESP32S3_RTCIO_IRQ
	bool "RTC IO interrupts"
	default n
	---help---
		Enable support for RTC peripherals interrupts.


menu "SPI configuration"
	depends on ESP32S3_SPI

choice
	prompt "SPI I/O Mode"
	default ESP32S3_SPI_IO_SPI

config ESP32S3_SPI_IO_SPI
	bool "SPI (4-line)"

config ESP32S3_SPI_IO_QIO
	bool "QIO (6-line)"

endchoice # SPI I/O Mode

config ESP32S3_SPI_SWCS
	bool "SPI software CS"
	default n
	depends on ESP32S3_SPI_IO_SPI
	---help---
		Use SPI software CS.

config ESP32S3_SPI_UDCS
	bool "User defined CS"
	default n
	depends on ESP32S3_SPI_SWCS
	---help---
		Use user-defined CS.

config ESP32S3_SPI_DMA
	bool "SPI use GDMA"
	default n
	select ESP32S3_DMA
	---help---
		Enable support for transfers using the GDMA engine.

config ESP32S3_SPI_DMA_BUFSIZE
	int "SPI Master GDMA buffer size"
	default 2048
	depends on ESP32S3_SPI_DMA
	---help---
		This is used to calculate and allocate DMA description buffer,
		not really allocate TX/RX buffer.

config ESP32S3_SPI_DMATHRESHOLD
	int "SPI Master GDMA threshold"
	default 64
	depends on ESP32S3_SPI_DMA && ESP32S3_SPI_IO_SPI
	---help---
		When SPI GDMA is enabled, GDMA transfers whose size are below the
		defined threshold will be performed by polling logic.

config ESP32S3_SPI_SLAVE_BUFSIZE
	int "SPI Slave buffer size"
	default 2048
	depends on SPI_SLAVE

config ESP32S3_SPI2_CSPIN
	int "SPI2 CS Pin"
	default 10
	range 0 48

config ESP32S3_SPI2_CLKPIN
	int "SPI2 CLK Pin"
	default 12
	range 0 48

config ESP32S3_SPI2_MOSIPIN
	int "SPI2 MOSI Pin"
	default 11
	range 0 48

config ESP32S3_SPI2_MISOPIN
	int "SPI2 MISO Pin"
	default 13
	range 0 48

config ESP32S3_SPI2_IO2PIN
	int "SPI2 IO2 Pin"
	default 14
	range 0 48
	depends on ESP32S3_SPI_IO_QIO

config ESP32S3_SPI2_IO3PIN
	int "SPI2 IO3 Pin"
	default 9
	range 0 48
	depends on ESP32S3_SPI_IO_QIO

config ESP32S3_SPI3_CSPIN
	int "SPI3 CS Pin"
	default 10
	range 0 48

config ESP32S3_SPI3_CLKPIN
	int "SPI3 CLK Pin"
	default 6
	range 0 48

config ESP32S3_SPI3_MOSIPIN
	int "SPI3 MOSI Pin"
	default 7
	range 0 48

config ESP32S3_SPI3_MISOPIN
	int "SPI3 MISO Pin"
	default 2
	range 0 48

config ESP32S3_SPI3_IO2PIN
	int "SPI3 IO2 Pin"
	default 3
	range 0 48
	depends on ESP32S3_SPI_IO_QIO

config ESP32S3_SPI3_IO3PIN
	int "SPI3 IO3 Pin"
	default 4
	range 0 48
	depends on ESP32S3_SPI_IO_QIO

endmenu # SPI configuration

menu "UART Configuration"
	depends on ESP32S3_UART

if ESP32S3_UART0

config ESP32S3_UART0_RS485
	bool "RS-485 on UART0"
	default n
	---help---
		Enable RS-485 interface on UART0. Your board config will have to
		provide GPIO_UART0_RS485_DIR pin definition.

config ESP32S3_UART0_RS485_DIR_PIN
	int "UART0 RS-485 DIR pin"
	default 25
	range 0 48
	depends on ESP32S3_UART0_RS485
	---help---
		DIR pin for RS-485 on UART0. This pin will control the RS485 enable
		TX of the RS485 transceiver.

config ESP32S3_UART0_RS485_DIR_POLARITY
	int "UART0 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on ESP32S3_UART0_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART0. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config ESP32S3_UART0_TXPIN
	int "UART0 Tx Pin"
	default 43
	range 0 48

config ESP32S3_UART0_RXPIN
	int "UART0 Rx Pin"
	default 44
	range 0 48

config ESP32S3_UART0_RTSPIN
	int "UART0 RTS Pin"
	depends on SERIAL_IFLOWCONTROL
	default 15
	range 0 48

config ESP32S3_UART0_CTSPIN
	int "UART0 CTS Pin"
	depends on SERIAL_OFLOWCONTROL
	default 16
	range 0 48

endif # ESP32S3_UART0

if ESP32S3_UART1

config ESP32S3_UART1_RS485
	bool "RS-485 on UART1"
	default n
	---help---
		Enable RS-485 interface on UART1. Your board config will have to
		provide GPIO_UART1_RS485_DIR pin definition.

config ESP32S3_UART1_RS485_DIR_PIN
	int "UART1 RS-485 DIR pin"
	default 26
	range 0 48
	depends on ESP32S3_UART1_RS485
	---help---
		DIR pin for RS-485 on UART1. This pin will control the RS485 enable
		TX of the RS485 transceiver.

config ESP32S3_UART1_RS485_DIR_POLARITY
	int "UART1 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on ESP32S3_UART1_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART1. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config ESP32S3_UART1_TXPIN
	int "UART1 Tx Pin"
	default 17
	range 0 48

config ESP32S3_UART1_RXPIN
	int "UART1 Rx Pin"
	default 18
	range 0 48

config ESP32S3_UART1_RTSPIN
	int "UART1 RTS Pin"
	depends on SERIAL_IFLOWCONTROL
	default 19
	range 0 48

config ESP32S3_UART1_CTSPIN
	int "UART1 CTS Pin"
	depends on SERIAL_OFLOWCONTROL
	default 20
	range 0 48

endif # ESP32S3_UART1

if ESP32S3_UART2

config ESP32S3_UART2_RS485
	bool "RS-485 on UART2"
	default n
	---help---
		Enable RS-485 interface on UART2. Your board config will have to
		provide GPIO_UART2_RS485_DIR pin definition.

config ESP32S3_UART2_RS485_DIR_PIN
	int "UART2 RS-485 DIR pin"
	default 27
	range 0 48
	depends on ESP32S3_UART2_RS485
	---help---
		DIR pin for RS-485 on UART2. This pin will control the RS485 enable
		TX of the RS485 transceiver.

config ESP32S3_UART2_RS485_DIR_POLARITY
	int "UART2 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on ESP32S3_UART2_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART2. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config ESP32S3_UART2_TXPIN
	int "UART2 Tx Pin"
	default 21
	range 0 48

config ESP32S3_UART2_RXPIN
	int "UART2 Rx Pin"
	default 22
	range 0 48

config ESP32S3_UART2_RTSPIN
	int "UART2 RTS Pin"
	depends on SERIAL_IFLOWCONTROL
	default 23
	range 0 48

config ESP32S3_UART2_CTSPIN
	int "UART2 CTS Pin"
	depends on SERIAL_OFLOWCONTROL
	default 24
	range 0 48

endif # ESP32S3_UART2

endmenu # UART Configuration

menu "I2C Configuration"
	depends on ESP32S3_I2C

if ESP32S3_I2C0

config ESP32S3_I2C0_SCLPIN
	int "I2C0 SCL Pin"
	default 2
	range 0 48

config ESP32S3_I2C0_SDAPIN
	int "I2C0 SDA Pin"
	default 1
	range 0 48

endif # ESP32S3_I2C0

if ESP32S3_I2C1

config ESP32S3_I2C1_SCLPIN
	int "I2C1 SCL Pin"
	default 5
	range 0 48

config ESP32S3_I2C1_SDAPIN
	int "I2C1 SDA Pin"
	default 4
	range 0 48

endif # ESP32S3_I2C1

config ESP32S3_I2CTIMEOSEC
	int "Timeout seconds"
	default 0

config ESP32S3_I2CTIMEOMS
	int "Timeout milliseconds"
	default 500

endmenu # I2C Configuration

menu "TWAI driver options"
	depends on ESP32S3_TWAI

if ESP32S3_TWAI

config ESP32S3_TWAI_TXPIN
	int "TWAI TX Pin"
	default 0

config ESP32S3_TWAI_RXPIN
	int "TWAI RX Pin"
	default 2

config ESP32S3_TWAI_BITRATE
	int "TWAI bitrate"
	default 1000000
	---help---
		TWAI bit rate.

config ESP32S3_TWAI_SAMPLEP
	int "TWAI sample point"
	default 80
	---help---
		TWAI sample point location as a percent value.

config ESP32S3_TWAI_SJW
	int "TWAI synchronization jump width"
	default 3
	---help---
		SJW limits the number of Time Quanta corrections during bit
		Resynchronization.

config ESP32S3_TWAI_SAM
	bool "TWAI sampling"
	default n
	---help---
		The bus is sampled 3 times (recommended for low to medium speed buses
		to spikes on the bus-line).

endif # ESP32S3_TWAI

config ESP32S3_TWAI_REGDEBUG
	bool "TWAI register level debug"
	depends on DEBUG_CAN_INFO
	default n
	---help---
		Output detailed register-level TWAI debug information. Requires also
		CONFIG_DEBUG_CAN_INFO.

endmenu #ESP32S3_TWAI

menu "Wi-Fi Configuration"
	depends on ESP32S3_WIFI

menu "ESP WPA-Supplicant"

config WPA_WAPI_PSK
	bool "Enable WAPI PSK support"
	default n
	---help---
		Select this option to enable WAPI-PSK
		which is a Chinese National Standard Encryption for Wireless LANs (GB 15629.11-2003).

config WPA_SUITE_B_192
	bool "Enable NSA suite B support with 192-bit key"
	default n
	select ESP_WIFI_GCMP_SUPPORT
	select ESP_WIFI_GMAC_SUPPORT
	---help---
		Select this option to enable 192-bit NSA suite-B.
		This is necessary to support WPA3 192-bit security.

config ESP_WPA_DEBUG_PRINT
	bool "Print debug messages from Espressif's WPA Supplicant"
	default n
	---help---
		Select this option to print logging information from WPA supplicant,
		this includes handshake information and key hex dumps depending
		on the project logging level.

		Enabling this could increase the build size ~60kb
		depending on the project logging level.

endmenu # ESP WPA-Supplicant

choice
	prompt "ESP32S3 Wi-Fi mode"
	default ESP32S3_WIFI_STATION

config ESP32S3_WIFI_STATION
	bool "Station mode"

config ESP32S3_WIFI_SOFTAP
	bool "SoftAP mode"

config ESP32S3_WIFI_STATION_SOFTAP
	bool "Station + SoftAP"

endchoice # ESP32S3 Wi-Fi mode

config ESP32S3_WIFI_STATIC_RXBUF_NUM
	int "Wi-Fi static RX buffer number"
	default 10

config ESP32S3_WIFI_DYNAMIC_RXBUF_NUM
	int "Wi-Fi dynamic RX buffer number"
	default 32

config ESP32S3_WIFI_DYNAMIC_TXBUF_NUM
	int "Wi-Fi dynamic TX buffer number"
	default 32

config ESP32S3_WIFI_TX_AMPDU
	bool "Wi-Fi TX AMPDU"
	default y

config ESP32S3_WIFI_RX_AMPDU
	bool "Wi-Fi RX AMPDU"
	default y

config ESP32S3_WIFI_RXBA_AMPDU_WZ
	int "Wi-Fi RX BA AMPDU windown size"
	default 6

config ESP_WIFI_GCMP_SUPPORT
	bool "WiFi GCMP Support(GCMP128 and GCMP256)"
	default n
	---help---
		Select this option to enable GCMP support. GCMP support is compulsory for WiFi Suite-B support.

config ESP_WIFI_GMAC_SUPPORT
	bool "WiFi GMAC Support(GMAC128 and GMAC256)"
	default n
	---help---
		Select this option to enable GMAC support. GMAC support is compulsory for WiFi 192-bit certification.

config ESP32S3_WIFI_CONNECT_TIMEOUT
	int "Connect timeout in second"
	default 10
	---help---
		Max waiting time of connecting to AP.

config ESP32S3_WIFI_SCAN_RESULT_SIZE
	int "Scan result buffer"
	default 4096
	---help---
		Maximum scan result buffer size.

config ESP32S3_WIFI_STA_DISCONNECT_PM
	bool "Power Management for station when disconnected"
	default y
	---help---
		Select this option to enable power management for station when disconnected.
		Chip will do modem-sleep when RF module is not in use anymore.

choice ESP32S3_POWER_SAVE_MODE
	prompt "Wi-Fi Power save mode"
	default ESP32S3_POWER_SAVE_MIN_MODEM if ESP32S3_WIFI_BT_COEXIST
	default ESP32S3_POWER_SAVE_NONE
	---help---
		Wi-Fi supports the Modem-sleep mode which refers to the legacy power-saving mode in the IEEE 802.11 protocol.
		Modem-sleep mode works in station-only mode and the station must connect to the AP first. If the Modem-sleep
		mode is enabled, station will switch between active and sleep state periodically. In sleep state, RF, PHY and
		BB are turned off in order to reduce power consumption. Station can keep connection with AP in modem-sleep mode.

		Modem-sleep mode includes minimum and maximum power-saving modes.

		In minimum power-saving mode, station wakes
		up every DTIM to receive beacon. Broadcast data will not be lost because it is transmitted after DTIM.
		However, it cannot save much more power if DTIM is short for DTIM is determined by AP.

		In maximum power-saving mode, station wakes up in every listen interval to receive beacon. This listen interval
		can be set to be longer than the AP DTIM period. Broadcast data may be lost because station may be in sleep
		state at DTIM time. If listen interval is longer, more power is saved, but broadcast data is more easy to lose.
		Listen interval can be configured by setting ESP32S3_WIFI_LISTEN_INTERVAL.

		ESP32S3_POWER_SAVE_NONE disables Modem-sleep mode entirely. Disabling it increases power consumption, but
		minimizes the delay in receiving Wi-Fi data in real time. When Modem-sleep mode is enabled, the delay in
		receiving Wi-Fi data may be the same as the DTIM cycle (minimum power-saving mode) or the listening interval
		(maximum power-saving mode). Setting ESP32S3_POWER_SAVE_NONE is suitable when high throughput is required.

config ESP32S3_POWER_SAVE_NONE
	bool "No power save"

config ESP32S3_POWER_SAVE_MIN_MODEM
	bool "Minimum modem power saving."

config ESP32S3_POWER_SAVE_MAX_MODEM
	bool "Maximum modem power saving"

endchoice # ESP32S3_POWER_SAVE_MODE

config ESP32S3_WIFI_LISTEN_INTERVAL
	int "Wi-Fi listen interval"
	depends on ESP32S3_POWER_SAVE_MAX_MODEM
	default 3
	---help---
		Interval for station to listen to beacon from AP. The unit of listen interval is one beacon interval.
		For example, if beacon interval is 100 ms and listen interval is 3, the interval for station to listen
		to beacon is 300 ms.

endmenu # ESP32S3_WIFI

menu "BLE Configuration"
	depends on ESP32S3_BLE

config ESP32S3_BLE_TTY_NAME
	string "BLE TTY device name"
	default "/dev/ttyHCI0"
	depends on UART_BTH4

config ESP32S3_BLE_TASK_STACK_SIZE
	int "Controller task stack size"
	default 4096

config ESP32S3_BLE_TASK_PRIORITY
	int "Controller task priority"
	default 253

config ESP32S3_BLE_INTERRUPT_SAVE_STATUS
	int "Number of interrupt save status"
	default 3
	---help---
		Number of interrupt save status variables to keep track. Increase it if any related bug is found.

endmenu # BLE Configuration

menu "PHY"
	depends on ESP32S3_PARTITION_TABLE

menuconfig ESP32S3_PHY_INIT_DATA_IN_PARTITION
	bool "Use a partition to store PHY init data"
	default n
	---help---
		If enabled, PHY init data will be loaded from a partition. Otherwise,
		PHY init data will be embedded into the application binary.

		When using a custom partition table, make sure that the PHY data
		partition is included (type: 'data', subtype: 'phy').

		If PHY init data is stored in a partition, it has to be flashed there,
		otherwise runtime error will occur.

config ESP32S3_PHY_DEFAULT_INIT_IF_INVALID
	bool "Reset default PHY init data if invalid"
	default n
	depends on ESP32S3_PHY_INIT_DATA_IN_PARTITION
	---help---
		If enabled, PHY init data will be restored to default if
		it cannot be verified successfully to avoid endless bootloops.

		If unsure, choose 'n'.

if ESP32S3_PHY_INIT_DATA_IN_PARTITION

config ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA
	bool "Support multiple PHY init data bin"
	depends on ESP32S3_PHY_INIT_DATA_IN_PARTITION
	default n
	---help---
		If enabled, the corresponding PHY init data type can be automatically switched
		according to the country code. China's PHY init data bin is used by default.
		Can be modified by country information in API esp_wifi_set_country().
		The priority of switching the PHY init data type is:
		1. Country configured by API esp_wifi_set_country()
		and the parameter policy is WIFI_COUNTRY_POLICY_MANUAL.
		2. Country notified by the connected AP.
		3. Country configured by API esp_wifi_set_country()
		and the parameter policy is WIFI_COUNTRY_POLICY_AUTO.

config ESP32S3_PHY_INIT_DATA_ERROR
	bool "Terminate operation when PHY init data error"
	depends on ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA
	default n
	---help---
		If enabled, when an error occurs while the PHY init data is updated,
		the program will terminate and restart.
		If not enabled, the PHY init data will not be updated when an error occurs.

endif

endmenu # PHY

menu "Timer/Counter Configuration"
	depends on ESP32S3_TIMER

config ESP32S3_ONESHOT
	bool "One-shot wrapper"
	default n
	---help---
		Enable a wrapper around the low level timer/counter functions to
		support one-shot timer.

config ESP32S3_FREERUN
	bool "Free-running wrapper"
	default n
	---help---
		Enable a wrapper around the low level timer/counter functions to
		support a free-running timer.

endmenu # Timer/Counter Configuration

menu "RTC Configuration"
	depends on ESP32S3_RTC

choice ESP32S3_RTC_CLK_SRC
	prompt "RTC clock source"
	default ESP32S3_RTC_CLK_INT_RC
	---help---
		Choose which clock is used as RTC clock source.

		- "Internal 150kHz oscillator" option provides lowest deep sleep current
			consumption, and does not require extra external components. However
			frequency stability with respect to temperature is poor, so time may
			drift in deep/light sleep modes.
		- "External 32kHz crystal" provides better frequency stability, at the
			expense of slightly higher (1uA) deep sleep current consumption.
		- "External 32kHz oscillator" allows using 32kHz clock generated by an
			external circuit. In this case, external clock signal must be connected
			to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
			and <1V in case of square wave signal. Common mode voltage should be
			0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
			Additionally, 1nF capacitor must be connected between 32K_XP pin and
			ground. 32K_XP pin can not be used as a GPIO in this case.
		- "Internal 8.5MHz oscillator divided by 256" option results in higher
			deep sleep current (by 5uA) but has better frequency stability than
			the internal 150kHz oscillator. It does not require external components.

config ESP32S3_RTC_CLK_INT_RC
	bool "Internal 150kHz RC oscillator"

config ESP32S3_RTC_CLK_EXT_XTAL
	bool "External 32kHz crystal"
	select ESP_SYSTEM_RTC_EXT_XTAL

config ESP32S3_RTC_CLK_EXT_OSC
	bool "External 32kHz oscillator at 32K_XN pin"
	select ESP_SYSTEM_RTC_EXT_XTAL

config ESP32S3_RTC_CLK_INT_8MD256
	bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"

endchoice

config ESP32S3_SYSTEM_BBPLL_RECALIB
	bool "Re-calibration BBPLL at startup"
	default y
	---help---
		This configuration helps to address an BBPLL inaccurate issue when boot from certain
		bootloader version, which may increase about the boot-up time by about 200 us.
		Disable this when your bootloader is built with ESP-IDF version v5.2 and above.

endmenu # "RTC Configuration"


menu "Real-Time Timer Configuration"
	depends on ESP32S3_RT_TIMER

config ESP32S3_RT_TIMER_TASK_NAME
	string "Real-Time Timer task name"
	default "rt_timer"

config ESP32S3_RT_TIMER_TASK_PRIORITY
	int "Real-Time Timer task priority"
	default 223
	---help---
		Priority level of the RT Timer task.
		Must be lower than the SCHED_HPWORKPRIORITY.

config ESP32S3_RT_TIMER_TASK_STACK_SIZE
	int "Real-Time Timer task stack size"
	default 2048

endmenu # Real-Time Timer Configuration

config ESP32S3_TICKLESS
	bool "Enable Tickless OS"
	default n
	select ARCH_HAVE_TICKLESS
	select SCHED_TICKLESS

config ESP32S3_SPIFLASH
	bool "SPI Flash MTD Partition"
	default n

menu "SPI Flash configuration"

choice ESP32S3_FLASH_MODE
	prompt "SPI Flash mode"
	default ESP32S3_FLASH_MODE_DIO
	---help---
		These options control how many I/O pins are used for communication
		with the attached SPI Flash chip.
		The option selected here is then used by esptool when flashing.

config ESP32S3_FLASH_MODE_DIO
	bool "Dual IO (DIO)"

config ESP32S3_FLASH_MODE_DOUT
	bool "Dual Output (DOUT)"

config ESP32S3_FLASH_MODE_QIO
	bool "Quad IO (QIO)"

config ESP32S3_FLASH_MODE_QOUT
	bool "Quad Output (QOUT)"

config ESP32S3_FLASH_MODE_OCT
	bool "Octal"

endchoice # ESP32S3_FLASH_MODE

choice ESP32S3_FLASH_FREQ
	prompt "SPI Flash frequency"
	default ESP32S3_FLASH_FREQ_40M
	---help---
		SPI Flash frequency

config ESP32S3_FLASH_FREQ_120M
	bool "120 MHz"

config ESP32S3_FLASH_FREQ_80M
	bool "80 MHz"

config ESP32S3_FLASH_FREQ_40M
	bool "40 MHz"

config ESP32S3_FLASH_FREQ_20M
	bool "20 MHz"

endchoice # ESP32S3_FLASH_FREQ

config ESP32S3_FLASH_FREQ
	int
	default 120 if ESP32S3_FLASH_FREQ_120M
	default 80 if ESP32S3_FLASH_FREQ_80M
	default 40 if ESP32S3_FLASH_FREQ_40M
	default 20 if ESP32S3_FLASH_FREQ_20M

choice ESP32S3_FLASH_SAMPLE_MODE
	prompt "Flash Sampling Mode"
	default ESP32S3_FLASH_SAMPLE_MODE_DTR if ESP32S3_FLASH_MODE_OCT
	default ESP32S3_FLASH_SAMPLE_MODE_STR if !ESP32S3_FLASH_MODE_OCT

config ESP32S3_FLASH_SAMPLE_MODE_DTR
	depends on ESP32S3_FLASH_MODE_OCT
	bool "DTR Mode"
config ESP32S3_FLASH_SAMPLE_MODE_STR
	bool "STR Mode"

endchoice # ESP32S3_FLASH_SAMPLE_MODE

config ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
	bool "Don't use SPI flash driver in ROM"
	default n
	---help---
		Use source code for SPI flash driver instead of functions
		in ROM.

config ESP32S3_SPI_FLASH_USE_32BIT_ADDRESS
	bool "SPI flash uses 32-bit address"
	default n
	select ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE
	---help---
		SPI flash driver in ROM only support 24-bit address access,
		if select the option, it will force to use source code instead
		of functions in ROM, so that SPI flash driver can access full
		32-bit address.

config ESP32S3_HAVE_OTA_PARTITION
	bool
	default n

if ESP32S3_HAVE_OTA_PARTITION

comment "Application Image OTA Update support"

config ESP32S3_OTA_PRIMARY_SLOT_OFFSET
	hex "Application image primary slot offset"
	default 0x10000

config ESP32S3_OTA_PRIMARY_SLOT_DEVPATH
	string "Application image primary slot device path"
	default "/dev/ota0"

config ESP32S3_OTA_SECONDARY_SLOT_OFFSET
	hex "Application image secondary slot offset"
	default 0x110000

config ESP32S3_OTA_SECONDARY_SLOT_DEVPATH
	string "Application image secondary slot device path"
	default "/dev/ota1"

config ESP32S3_OTA_SLOT_SIZE
	hex "Application image slot size (in bytes)"
	default 0x100000

config ESP32S3_OTA_SCRATCH_OFFSET
	hex "Scratch partition offset"
	default 0x210000

config ESP32S3_OTA_SCRATCH_SIZE
	hex "Scratch partition size"
	default 0x40000

config ESP32S3_OTA_SCRATCH_DEVPATH
	string "Scratch partition device path"
	default "/dev/otascratch"

endif # ESP32S3_HAVE_OTA_PARTITION

if ESP32S3_SPIFLASH

comment "General storage MTD configuration"

config ESP32S3_MTD
	bool "MTD driver"
	default y
	select MTD
	select MTD_BYTE_WRITE
	select MTD_PARTITION
	---help---
		Initialize an MTD driver for the ESP32-S3 SPI Flash, which will
		add an entry at /dev for application access from userspace.

config ESP32S3_SPIFLASH_MTD_BLKSIZE
	int "Storage MTD block size"
	default 256
	depends on ESP32S3_MTD

config ESP32S3_STORAGE_MTD_DEBUG
	bool "Storage MTD Debug"
	default n
	depends on ESP32S3_MTD && DEBUG_FS_INFO
	---help---
		If this option is enabled, Storage MTD driver read and write functions
		will output input parameters and return values (if applicable).

config ESP32S3_SPIFLASH_OP_TASK_STACKSIZE
	int "The SPI flash operation task stack size"
	default 768
	depends on SMP
	---help---
		When SMP is enabled, it is needed to create two tasks (one for each
		core) to be able to run IRAM-enabled interrupts. These tasks ensures
		that the core that isn't performing the SPI flash operation is able
		to disable non-IRAM interrupts and wait for the SPI flash operation
		to be finished.

config ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK
	bool "Support PSRAM As Task Stack"
	default n
	depends on ESP32S3_SPIRAM
	select SCHED_LPWORK
	---help---
		Enable this option, Tasks which use PSRAM as stack
		can do SPI Flash read/write/erase/map/unmap. Otherwise,
		it may cause exception, the root cause is as following:
			1. When operating SPI flash, cache is also disable,
		   		then software can't access PSRAM by data cache.
			2. SPI flash read/write/erase functions have instruction like
				stack-pop and stack-push which may use stack buffer which is
		   		PSRAM space or load/store temp variables which locate in PSRAM space too.
			3. Once operation in step 2 triggers, CPU will trigger exception.
		So related SPI flash functions should be sent and run in tasks which use SRAM as task stack.

if ESP32S3_APP_FORMAT_LEGACY

comment "Partition Table configuration"

config ESP32S3_PARTITION_TABLE
	bool "Create MTD partitions from Partition Table"
	default n
	depends on ESP32S3_MTD && ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
	---help---
		Decode partition table and initialize partitions as MTD.

config ESP32S3_PARTITION_MOUNTPT
	string "Partition mount point"
	default "/dev/esp/partition/"
	depends on ESP32S3_PARTITION_TABLE

endif # ESP32S3_APP_FORMAT_LEGACY

endif # ESP32S3_SPIFLASH

endmenu # SPI Flash configuration

menu "LEDC Configuration"
	depends on ESP32S3_LEDC

menuconfig ESP32S3_LEDC_TIM0
	bool "Timer 0"
	default n

if ESP32S3_LEDC_TIM0

config ESP32S3_LEDC_TIM0_CHANNELS
	int "Number of Timer 0 channels"
	default 2

endif # ESP32S3_LEDC_TIM0

menuconfig ESP32S3_LEDC_TIM1
	bool "Timer 1"
	default n

if ESP32S3_LEDC_TIM1

config ESP32S3_LEDC_TIM1_CHANNELS
	int "Number of Timer 1 channels"
	default 2

endif # ESP32S3_LEDC_TIM1

menuconfig ESP32S3_LEDC_TIM2
	bool "Timer 2"
	default n

if ESP32S3_LEDC_TIM2

config ESP32S3_LEDC_TIM2_CHANNELS
	int "Number of Timer 2 channels"
	default 2

endif # ESP32S3_LEDC_TIM2

menuconfig ESP32S3_LEDC_TIM3
	bool "Timer 3"
	default n

if ESP32S3_LEDC_TIM3

config ESP32S3_LEDC_TIM3_CHANNELS
	int "Number of Timer 3 channels"
	default 2

endif # ESP32S3_LEDC_TIM2

config ESP32S3_LEDC_CHANNEL0_PIN
	int "Channel 0 pin"
	default 2

config ESP32S3_LEDC_CHANNEL1_PIN
	int "Channel 1 pin"
	default 3

config ESP32S3_LEDC_CHANNEL2_PIN
	int "Channel 2 pin"
	default 4

config ESP32S3_LEDC_CHANNEL3_PIN
	int "Channel 3 pin"
	default 5

config ESP32S3_LEDC_CHANNEL4_PIN
	int "Channel 4 pin"
	default 6

config ESP32S3_LEDC_CHANNEL5_PIN
	int "Channel 5 pin"
	default 7

config ESP32S3_LEDC_CHANNEL6_PIN
	int "Channel 6 pin"
	default 8

config ESP32S3_LEDC_CHANNEL7_PIN
	int "Channel 7 pin"
	default 9

endmenu # LEDC configuration

menu "USB OTG Configuration"
	depends on ESP32S3_OTG

choice
	prompt "USB OTG Mode"
	default ESP32S3_OTG_DEVICE

config ESP32S3_OTG_DEVICE
	bool "Device"
	select USBDEV

endchoice # USB OTG Mode

if ESP32S3_OTG_DEVICE

config ESP32S3_OTG_ENDPOINT_NUM
	int "Additional Endpoint Number Except Endpoint 0"
	range 0 6
	default 3

endif # ESP32S3_OTG_DEVICE

config ESP32S3_OTG_DEBUG_REGISTER
	bool "Debug Register Get/Set"
	default n
	depends on DEBUG_USB_INFO

endmenu # USB OTG Configuration

menu "LCD Controller Configuration"
	depends on ESP32S3_LCD

menu "LCD Pin Configuration"

config ESP32S3_LCD_PCLK_PIN
	int "LCD Pixel Clock Signal Pin"
	default 9

config ESP32S3_LCD_VSYNC_PIN
	int "LCD Vertical Synchronization Pin"
	default 3

config ESP32S3_LCD_HSYNC_PIN
	int "LCD Horizontal Synchronization Pin"
	default 46

config ESP32S3_LCD_HE_PIN
	int "LCD Horizontal Enable Pin"
	default 17

config ESP32S3_LCD_DATA0_PIN
	int "LCD Parallel Output Data Bit-0 Pin"
	default 10

config ESP32S3_LCD_DATA1_PIN
	int "LCD Parallel Output Data Bit-1 Pin"
	default 11

config ESP32S3_LCD_DATA2_PIN
	int "LCD Parallel Output Data Bit-2 Pin"
	default 12

config ESP32S3_LCD_DATA3_PIN
	int "LCD Parallel Output Data Bit-3 Pin"
	default 13

config ESP32S3_LCD_DATA4_PIN
	int "LCD Parallel Output Data Bit-4 Pin"
	default 14

config ESP32S3_LCD_DATA5_PIN
	int "LCD Parallel Output Data Bit-5 Pin"
	default 21

config ESP32S3_LCD_DATA6_PIN
	int "LCD Parallel Output Data Bit-6 Pin"
	default 47

config ESP32S3_LCD_DATA7_PIN
	int "LCD Parallel Output Data Bit-7 Pin"
	default 48

config ESP32S3_LCD_DATA8_PIN
	int "LCD Parallel Output Data Bit-8 Pin"
	default 45

config ESP32S3_LCD_DATA9_PIN
	int "LCD Parallel Output Data Bit-9 Pin"
	default 38

config ESP32S3_LCD_DATA10_PIN
	int "LCD Parallel Output Data Bit-10 Pin"
	default 39

config ESP32S3_LCD_DATA11_PIN
	int "LCD Parallel Output Data Bit-11 Pin"
	default 40

config ESP32S3_LCD_DATA12_PIN
	int "LCD Parallel Output Data Bit-12 Pin"
	default 41

config ESP32S3_LCD_DATA13_PIN
	int "LCD Parallel Output Data Bit-13 Pin"
	default 42

config ESP32S3_LCD_DATA14_PIN
	int "LCD Parallel Output Data Bit-14 Pin"
	default 2

config ESP32S3_LCD_DATA15_PIN
	int "LCD Parallel Output Data Bit-15 Pin"
	default 1

endmenu

menu "LCD Display Configuration"
	depends on ESP32S3_LCD

config ESP32S3_LCD_VRES
	int "LCD Vertical Resolution"
	default 480

config ESP32S3_LCD_HRES
	int "LCD Horizontal Resolution"
	default 480

config ESP32S3_LCD_CLOCK_MHZ
	int "LCD Pixel Clock Frequency in MHz"
	default 2

config ESP32S3_LCD_VFRONTPORCH
	int "LCD Vertical Front Porch"
	default 40

config ESP32S3_LCD_VBACKPORCH
	int "LCD Vertical Back Porch"
	default 20

config ESP32S3_LCD_VPULSEWIDTH
	int "LCD Vertical Pulse Width"
	default 13

config ESP32S3_LCD_HFRONTPORCH
	int "LCD Horizontal Front Porch"
	default 40

config ESP32S3_LCD_HBACKPORCH
	int "LCD Horizontal Back Porch"
	default 20

config ESP32S3_LCD_HPULSEWIDTH
	int "LCD Horizontal Pulse Width"
	default 15

config ESP32S3_LCD_BUFFER_LAYERS
	int "LCD Buffer Layer Number"
	default 1

choice
	prompt "LCD Data Width"
	default ESP32S3_LCD_DATA_16BIT

config ESP32S3_LCD_DATA_16BIT
	bool "16-bit"

endchoice # LCD Data Width

endmenu

config ESP32S3_LCD_REGDEBUG
	bool "LCD Debug Registers"
	default n

endmenu

menu "Application Image Configuration"

choice
	prompt "Application Image Format"
	default ESP32S3_APP_FORMAT_LEGACY
	---help---
		Depending on the chosen 2nd stage bootloader, the application may
		be required to be perform a specific startup routine. Furthermore,
		the image binary must be formatted according to the definition from
		the 2nd stage bootloader.

config ESP32S3_APP_FORMAT_LEGACY
	bool "Legacy format"
	---help---
		This is the legacy application image format, as supported by the ESP-IDF
		2nd stage bootloader.

config ESP32S3_APP_FORMAT_MCUBOOT
	bool "MCUboot-bootable format"
	depends on !MCUBOOT_BOOTLOADER
	select ESP32S3_HAVE_OTA_PARTITION
	---help---
		The Espressif port of MCUboot supports the loading of unsegmented firmware
		images.

endchoice # Application Image Format

choice
	prompt "Source for bootloader binaries"
	default ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
	---help---
		Select the action to be taken by the build system for the
		"make bootloader" target.

config ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
	bool "Download prebuilt binaries"
	---help---
		The build system will download the prebuilt binaries from
		https://github.com/espressif/esp-nuttx-bootloader according to the chosen
		Application Image Format (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT)

config ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
	bool "Build binaries from source"
	---help---
		The build system will build all the required binaries from source. It will clone
		the https://github.com/espressif/esp-nuttx-bootloader repository and build a
		custom bootloader according to the chosen Application Image Format
		(ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) and partition information.

endchoice

choice
	prompt "Target slot for image flashing"
	default ESP32S3_ESPTOOL_TARGET_PRIMARY
	depends on ESP32S3_HAVE_OTA_PARTITION
	---help---
		Slot to which ESPTOOL will flash the generated binary image.

config ESP32S3_ESPTOOL_TARGET_PRIMARY
	bool "Application image primary slot"
	---help---
		This assumes that the generated image is already pre-validated.
		This is the recommended option for the initial stages of the
		application firmware image development.

config ESP32S3_ESPTOOL_TARGET_SECONDARY
	bool "Application image secondary slot"
	---help---
		The application needs to confirm the generated image as valid,
		otherwise the bootloader may consider it invalid and perform the
		rollback of the update after a reset.
		This is the choice most suitable for the development and verification
		of a secure firmware update workflow.

endchoice

config ESP32S3_MCUBOOT_VERSION
	string "MCUboot version"
	default "b206b99b1555ca15f790a3287e57dc98ef3df2ac"
	depends on ESP32S3_APP_FORMAT_MCUBOOT

config ESP32S3_APP_MCUBOOT_HEADER_SIZE
	int "Application image header size (in bytes)"
	default 32
	depends on ESP32S3_APP_FORMAT_MCUBOOT

config ESP32S3_PARTITION_TABLE_OFFSET
	hex "Partition Table offset"
	default 0x8000
	depends on ESP32S3_APP_FORMAT_LEGACY

config ESP32S3_KERNEL_OFFSET
	hex
	default 0x10000
	depends on ESP32S3_APP_FORMAT_LEGACY

if BUILD_PROTECTED

config ESP32S3_KERNEL_IMAGE_SIZE
	hex "Kernel Image Size"
	default 0x100000
	depends on ESP32S3_APP_FORMAT_LEGACY
	---help---
		Max size of the kernel image. This parameter is used to 1) write to
		the SPI flash, 2) calculate the offset for the user image and 3) set
		the KIROM, KDROM, UIROM and UDROM parameters in the linker. Please
		check boards/xtensa/esp32s3/common/scripts/protected_memory.ld for
		more information.

config ESP32S3_KERNEL_RAM_SIZE
	hex "Kernel Allocated RAM"
	default 0x29000
	range 0x10000 0x54700
	depends on ESP32S3_APP_FORMAT_LEGACY
	---help---
		Selects the amount of RAM available to the kernel from the total
		available amount (337,75KiB). The rest of the memory will be
		allocated to the user space. Respectively, this config will set the
		KDRAM and UDRAM parameters of the linker. Please check
		boards/xtensa/esp32s3/common/scripts/protected_memory.ld for more
		information.

endif # BUILD_PROTECTED

endmenu # Application Image Configuration

endif # ARCH_CHIP_ESP32S3
