--- cipher/cipher-gcm-armv8-aarch64-ce.S.orig	2016-11-12 10:39:35 UTC
+++ cipher/cipher-gcm-armv8-aarch64-ce.S
@@ -23,7 +23,7 @@
     defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \
     defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO)
 
-.arch armv8-a+crypto
+.cpu generic+simd+crypto
 
 .text
 
--- cipher/rijndael-armv8-aarch64-ce.S.orig	2017-01-18 11:28:40 UTC
+++ cipher/rijndael-armv8-aarch64-ce.S
@@ -23,7 +23,7 @@
     defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \
     defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO)
 
-.arch armv8-a+crypto
+.cpu generic+simd+crypto
 
 .text
 
--- cipher/sha1-armv8-aarch64-ce.S.orig	2016-11-12 10:39:35 UTC
+++ cipher/sha1-armv8-aarch64-ce.S
@@ -23,7 +23,7 @@
     defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \
     defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO) && defined(USE_SHA1)
 
-.arch armv8-a+crypto
+.cpu generic+simd+crypto
 
 .text
 
--- cipher/sha256-armv8-aarch64-ce.S.orig	2016-11-12 10:39:35 UTC
+++ cipher/sha256-armv8-aarch64-ce.S
@@ -23,7 +23,7 @@
     defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \
     defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO) && defined(USE_SHA256)
 
-.arch armv8-a+crypto
+.cpu generic+simd+crypto
 
 .text
 
--- configure.ac.orig	2017-01-18 11:37:00 UTC
+++ configure.ac
@@ -1623,7 +1623,7 @@ AC_CACHE_CHECK([whether GCC inline assem
           gcry_cv_gcc_inline_asm_aarch64_neon=no
           AC_COMPILE_IFELSE([AC_LANG_SOURCE(
           [[__asm__(
-                ".arch armv8-a\n\t"
+                ".cpu generic+simd\n\t"
                 "mov w0, \#42;\n\t"
                 "dup v0.8b, w0;\n\t"
                 "ld4 {v0.8b,v1.8b,v2.8b,v3.8b},[x0],\#32;\n\t"
@@ -1648,7 +1648,11 @@ AC_CACHE_CHECK([whether GCC inline assem
           gcry_cv_gcc_inline_asm_aarch64_crypto=no
           AC_COMPILE_IFELSE([AC_LANG_SOURCE(
           [[__asm__(
-                ".arch armv8-a+crypto\n\t"
+		 ".cpu generic+simd\n\t"
+
+		 "mov w0, \#42;\n\t"
+		 "dup v0.8b, w0;\n\t"
+		 "ld4 {v0.8b,v1.8b,v2.8b,v3.8b},[x0],\#32;\n\t"
 
                 "sha1h s0, s0;\n\t"
                 "sha1c q0, s0, v0.4s;\n\t"
